Dr. Ahmed G. Abo-Khalil

Electrical Engineering Department

FPGA

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.

FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"—somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

In addition to digital functions, some FPGAs have analog features. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow. Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed signal FPGAs" have integrated peripheral Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip.[5] Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

Office Hours

Monday 10 -2

Tuesday 10-12

Thursday 11-1

My Timetable


Contacts


email: [email protected]

[email protected]

Phone: 2570

Welcome

Welcome To Faculty of Engineering

Almajmaah University


IEEE


http://www.ieee.org/

/

Links of Interest


http://www.utk.edu/research/

http://science.doe.gov/grants/index.asp

http://www1.eere.energy.gov/vehiclesandfuels/

http://www.eere.energy.gov/


Travel Web Sites

http://www.hotels.com/

http://www.orbitz.com/

http://www.hotwire.com/us/index.jsp

http://www.kayak.com/

Blackboard

ستقام اختبارات الميدتيرم يوم الثلاثاء 26-6-1440

حسب الجدول المعلن بلوحات الاعلان

Summer training

The registration for summer training will start from 5th week of second semester

Academic advising

Class registration week 1

برنامج التجسير




إحصائية الموقع

عدد الصفحات: 2879

البحوث والمحاضرات: 1280

الزيارات: 60985