Dr. Ahmed G. Abo-Khalil

Electrical Engineering Department

Flag bits

An instruction cache requires only one flag bit per cache row entry: a valid bit. The valid bit indicates whether or not a cache block has been loaded with valid data.

On power-up, the hardware sets all the valid bits in all the caches to "invalid". Some systems also set a valid bit to "invalid" at other times -- such as when multi-master bus snooping hardware in the cache of one processor hears an address broadcast from some other processor, and realizes that certain data blocks in the local cache are now stale and should be marked invalid.

A data cache typically requires two flag bits per cache row entry: a valid bit and also a dirty bit. The dirty bit indicates whether that block has been unchanged since it was read from main memory -- "clean" -- or whether the processor has written data to that block (and the new value has not yet made it all the way to main memory) -- "dirty".

Office Hours

Monday 10 -2

Tuesday 10-12

Thursday 11-1

My Timetable


Contacts


email: [email protected]

[email protected]

Phone: 2570

Welcome

Welcome To Faculty of Engineering

Almajmaah University


IEEE


http://www.ieee.org/

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Links of Interest


http://www.utk.edu/research/

http://science.doe.gov/grants/index.asp

http://www1.eere.energy.gov/vehiclesandfuels/

http://www.eere.energy.gov/


Travel Web Sites

http://www.hotels.com/

http://www.orbitz.com/

http://www.hotwire.com/us/index.jsp

http://www.kayak.com/

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