EE207


Electrical Engineering Department

EE 207

Logic Design Lab 


Schedule:

Week #1

Introductory to Laboratory equipment and Basic Component

Week #2

Introduction to laboratory equipment and their use like ETS-5000 advance logical training system.

Week #3

Digital electronic training system, Connectivity of ICs, logic Gates,

equipment.

Week #4

Basic Logic Gates (OR, AND & NOT, NOR, NAND XOR & XNOR Gates)

Week #5

Mid-term Exam 1

Week #6

Boolean Functions

Week #7

Full & Half Adder

Week #8

Full & Half Subtractor

Week #9

Mid-term Exam 2

Week #10

Decoders & Encoders

Week #11

Week #12

Multiplexers & Magnitude Comparator

Week #13

Code Converters, Latches & Flip-Flops, Registers & Shift Registers.

Week #14

Week #15

General Revision

Week #16

Final Exam



Grading:

Mini Project, attendance, or Lab Poster            5%

Lab Reports                                                          15%

Quizzes                                                                  10%

Discipline in Lab                                                  10%

Mid-term  Exam                                                   20%

Final  Exam                                                           40%



Policies:

- You should be present from the first 5 minutes of the Lab; otherwise, you will miss the credit for discipline, and you will be marked as late. Being late two times equal to one absence

Lab reports must be handed to me in the following lecture. Otherwise, no need to submit it because I do not collect late reports.

If you miss 4 labs, you will FAIL (get: F), and will not be allowed to take the final exam.




الملفات المرفقة

Office Hours

Office Hours

Tuesday: 08:00 to 08:50 am

Wednesday: 10:00 to 11:40 am

Important Announcements

إعلان هام

Contact Information


E-mail: [email protected]

Office: 44-01-26, 1st Floor

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